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Correspondence should be addressed to Lukasz Lopacinski ; moc. This is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. A serial Reed-Solomon decoder requires a clock of Processing so fast streams on a state-of-the-art FPGA field programmable gate arrays requires a dedicated approach. Thus, the paper presents lightweight RS FEC engine, frames fragmentation, aggregation, and a protocol with selective fragment retransmission.
Moreover, redundancy added to the frames is adopted according to the channel BER by a dedicated link adaptation algorithm. At the end, ASIC synthesis results are presented including detailed statistics of consumed energy per bit. The fastest wireless technology available, based on wireless LAN Figure 1 depicts the demonstrator setup as investigated in the DFG. This paper describes research on the data link layer part of the demonstrator.
COM activity [ 3 ]. More information on the dedicated PHY fpga implementation of single bit error correction using crc throttle and baseband processing can be found in [ 4 — 6 ]. Table 1 summarizes selected transmission experiments performed in the terahertz band at the PHY layer. From the data link layer point of view, the research presented in [ 7 ] is especially interesting. The simulation uses Hamming 15, 11 channel coding with automatic repeat request ARQ.
Our paper proposes significantly more powerful error correction techniques, but also the consumed energy per processed bit is approx. We focus on the overall transmission efficiency and reduce the overall overhead induced by protocols. As a result of our work an FPGA based data link layer processor is presented. However, the access time to such memory is too slow. However, it will work inefficiently because the data link layer of wireless systems must cope with unpredictable bit error rates BERleading to more complex solutions [ 18 ].
The BER in wireless communication can vary by several orders of magnitude. Therefore, the FEC has to be adopted to the channel conditions. This increases the average code rate and compensates the unpredictable BER on wireless links. An additional difference between the optical and wireless communication is duplex switching.
Optical communication can use two separated fibers to perform uplink and downlink transmissions. Fpga implementation of single bit error correction using crc throttle transceivers are limited in this aspect. In most cases, half-duplex communication takes place. A radio can be in receive or transmit mode, but usually never in both states at the same time. In the other case it is not possible to achieve high efficiency. That significantly improves robustness and efficiency of the system.
Unfortunately, the FEC gain is very expensive in meaning of the processing effort. This chapter explains all necessary optimizations required for the implementation of the FPGA data link fpga implementation of single bit error correction using crc throttle processor Figure 2.
One of the main objectives is algorithms comparison according to the computational complexity, hardware resources, and processing latency.
Frame error rate depends mainly on BER and frame length. For a longer frame, the probability that at least one of the bits will be altered during transmission is higher, due to the channel impairments. Fewer bits in a frame reduce the number of possibilities for bit errors to occur. Thus, shorter fpga implementation of single bit error correction using crc throttle are preferred in a noisy channel. This observation leads to a frame-fragmentation concept.
Long frames can be split into several shorter frames [ 22 ] Figure 3. This operation improves frame error rate and data goodput Figure 4. If the retransmission process is taken into consideration ARQthen the probability of successful transmission of a payload encapsulated into smaller frames is higher than probability of transmission of the same payload encapsulated into longer frames.
The probability can be calculated by the following equation: Shorter frame achieves significantly higher probability of successful reception. Frames fragmentation improves transmission goodput by decreasing frames length in a noisy environment. This reduces frame error rate, but there are also negative aspects of this process. Increased number of frames requires more preambles generated on the PHY level. Each frame is extended by a PHY preamble to set correct RF-gain, synchronize the center frequency, and recover the data clock on the receiver side.
In this time, user data is not transmitted and the preamble is reducing the goodput. Therefore, the number of transmitted preambles and headers should be reduced.
The only way to do it is to extend the frame length as much as possible. This reduces the number of transmitted preambles and headers, but very long frames are not preferred in a noisy RF-environment due to increased frame error rate. This causes an impasse, but there is a possibility to reduce the number of transmitted preambles as well as reduce the logical frame size using frames aggregation and selective fragment retransmission [ 23 ] Figure 6.
The most important aspect of an aggregated frame is resistance to bit errors and reduced preamble-overhead. The fragments of the frame share a common preamble and header, but CRC fields are separate. The CRCs are recalculated for each fragment independently, which allows detection and retransmission of the defected parts individually Figure 7. Additionally, fragments length can be controlled on the fly according to the channel BER. In the compared group of algorithms, RS consumes usually fewer hardware resources than the Viterbi.
It means that RS obtains higher throughput per a single logic cell Table 3. This comparison shows the advantages of RS decoders, but the analysis fpga implementation of single bit error correction using crc throttle not correct in this case. Both algorithms are compared in typical configurations. The code rate of the Viterbi decoder is defined as and the code rate of the RS as.
Thus, the algorithms have different error correction capabilities and such a study is not reliable. Additionally, changing the code rates of the codes may significantly influence the decoding efficiency, and such modified algorithms may be ineffective in terms of obtained coding gain and consumed hardware resources. Moreover, decoding performance depends on the error type on the decoder input, and both solutions prefer different channel types. Thus, comparison of the hardware resources is difficult and can lead to wrong conclusions.
Therefore, in this paragraph, a different benchmark is used. Due to this reason, Table 3 gives an approximation of average throughput per single LUT of a half rate soft decision Viterbi decoder in comparison to a hard coding RSdecoder.
The normalized decoding throughput of the RS is 25 times higher than for the Viterbi. Error correction performance of the RS is limited but allows communicating over channels with for single errors.
The RSrequires less hardware resources than the soft decision decodable LDPCto achieve the same decoding throughput. The previous paragraph clearly shows that the soft decodable FEC methods require very high computation power. Moreover, we do not have a possibility to realize ADC that supports multibit quantization at the targeted data rate. The Viterbi decodable convolutional code with obtains poor error correction performance. If a channel with burst errors is considered Figure 9then the RS decoder achieves significantly higher error correction performance than the other algorithms.
It is important to emphasize the fact that the LDPC and Viterbi decoders use hard-decoded data input, and it is an untypical way of using the codes. Additionally, data bits are packed into bit symbols in the considered baseband [ 4 ].
Therefore, an interleaved calculation array of RS decoders has to be employed. IRS architecture has two advantages. Firstly, robustness against long-burst errors is improved Figure Due to the hardware issues of Virtex7 FPGA, there are advantages to keep the internal processing data buses bit wide. The main reason of it is hardware multiplexing supported by the FPGA hardware. It is possible to design an algorithm that finds a trade-off between the coding overhead and the demanded error correction performance.
The algorithm analyses the number of successfully delivered data fragments and the number of corrected errors in the fragments. When the goodput is degraded by losses of data, then the algorithm increases the FEC coding. It is important to define thresholds, when the FEC modes should be changed.
One of possible solutions is setting the thresholds to the code rates of the employed codes. If the percentage of successfully delivered data fragments is below the given values, then a code with a lower code rate is applied.
In short, the approach finds a compromise between RS overhead and the rate of the lost data fragments. The thresholds correspond to the code rates and define the upper boundaries of achievable goodput for the codes. Figure 12 explains the theory of operation of the algorithm. Figure 13 shows the results of the proposed approach the FPGA adjusts the redundancy in a range of 2—18 symbols per RS block.
More details about the implemented link adaptation fpga implementation of single bit error correction using crc throttle be found in our articles in [ 2132 ]. When fragmentation and aggregation are in use, the frame header is the most important part of the fpga implementation of single bit error correction using crc throttle. The situation deteriorates greatly fpga implementation of single bit error correction using crc throttle a bit error occurs in the frame header.
The header contains necessary information for frame decoding, for example, the length and FEC encoding method. Additionally, complexity of the frame-decoding pipeline is lower when the header is decoded immediately without a fpga implementation of single bit error correction using crc throttle.
For this purpose, an independent triple-modular redundancy decoder is proposed. It means that information from the header can be used immediately and frame buffering is fpga implementation of single bit error correction using crc throttle.
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