4 bit binary ripple countdown counter circuit
Synchronous counters eliminate the cumulative flip-flop delay seen in ripple counter. Each flip-flop is clocked by the same clock signal. Each gate selectively controls when each more significant bit flip-flop is to change state toggle on the next clock transition. Such control enable can be realized by setting, for example, the J and K inputs of a J-K flip-flop. Because of this control, the addition of a common clock will synchronize data transfer and all flip-flops will change state simultaneously.
The important feature of a synchronous counter is that the transitions of the individual flip-flops are synchronized to a master clock signal. J-K flip-flops are normally used in the synchronous counters due to the enabling controlling feature of the J and K inputs. There are two basic schemes for generating the J and K inputs. One of them is illustrated in the four-bit binary counter shown in Fig. Notice that the information to the J-K inputs is formed in a parallel fashion.
The counter is accordingly termed as synchronous parallel counter. In the parallel scheme the number of inputs to each AND gate increases linearly with the number of stages.
For this added expense one gets the fastest possible synchronous counting circuit. Synchronous counters use JK flip-flops, as the programmable J and K inputs allow the toggling of individual flip-flops to be enabled or disabled at various stages of the count. Synchronous counters therefore eliminate the clock ripple problem, as the operation of the circuit is synchronised to the CK pulses, rather than flip-flop outputs.
Notice that the CK input is applied to all the flip-flops in parallel. Therefore, as all the flip-flops receive a clock pulse at the same instant, some method must be used to prevent all the flip-flops changing state at the same time. This of course would result in the counter outputs simply toggling from all ones to all zeros, and back again with each clock pulse.
However, with JK flip-flops, when both J and K inputs are logic 1 the output toggles on each CK pulse, but when J and K are both at logic 0 no change takes place. The binary output is taken from the Q outputs of the flip-flops. Note that on FF0 the J and K inputs are permanently wired to logic 1, so Q 0 will change state toggle on each clock pulse. In adding a third flip flop to the counter however, direct connection from J and K to the previous Q 1 output would not give the correct count.
Because Q 1 is high at a count of 2 10 this would mean that FF2 would toggle on clock pulse three, as J2 and K2 would be high. Therefore clock pulse 3 would give a binary count of 2 or 7 10 instead of 4 To prevent this problem an AND gate is used, as shown in Fig. Only when the outputs are in this state will the next clock pulse toggle Q 2 to logic 1.
The outputs Q 0 and Q 1 will of course return to logic 0 on this pulse, so giving a count of 2 or 4 10 with Q 0 being the least significant bit. Q 3 therefore will not toggle to its high state until the eighth clock pulse, and will remain high until the sixteenth clock pulse.
After this pulse, all the Q outputs will return to zero. Note that for this basic form of the synchronous counter to work, the PR and CLR inputs must also be all at logic 1, their inactive state as shown in Fig.
Converting the synchronous up counter to count down is simply a matter of reversing the count. If all of the ones and zeros in the 0 to 15 10 sequence shown in Table 5.
As every Q output on the JK flip-flops has its complement on Q , all that is needed to convert the up counter in Fig. Each group of gates between successive flip-flops is in fact a modified data select circuit described in Combinational Logic Module 4.
This is necessary to provide the correct logic state for the next data selector. If the control input is at logic 1 then the CK pulse to the next flip-flop is fed from the Q output, making the counter an UP counter, but if the control input is 0 then CK pulses are fed from Q and the counter is a DOWN counter. When Q 1 and Q 3 are both at logic 1, the output terminal of the limit detection NAND gate LD1 will become logic 0 and reset all the flip-flop outputs to logic 0.
Because the first time Q 1 and Q 3 are both at logic 1 during a 0 to 15 10 count is at a count of ten 2 , this will cause the counter to count from 0 to 9 10 and then reset to 0, omitting 10 10 to 15 The circuit is therefore a BCD counter, an extremely useful device for driving numeric displays via a BCD to 7-segment decoder etc.
However by re-designing the gating system to produce logic 0 at the CLR inputs for a different maximum value, any count other than 0 to 15 can be achieved. If you already have a simulator such as Logisim installed on your computer, why not try designing an Octal up counter for example. Although synchronous counters can be, and are built from individual JK flip-flops, in many circuits they will be ether built into dedicated counter ICs, or into other large scale integrated circuits LSICs.
For many applications the counters contained within ICs have extra inputs and outputs added to increase the counters versatility.
The differences between many commercial counter ICs are basically the different input and output facilities offered. Some of which are described below.
There are two basic schemes for generating the J and K inputs. One of them is illustrated in the four-bit binary counter shown in Fig. Notice that the information to the J-K inputs is formed in a parallel fashion. The counter is accordingly termed as synchronous parallel counter.
In the parallel scheme the number of inputs to each AND gate increases linearly with the number of stages. For this added expense one gets the fastest possible synchronous counting circuit. If the J-K input information is formed from the output of the AND gate in the previous stage, one has a synchronous serial counter. Although the serial scheme is slower than the parallel scheme, the number of inputs to the AND gate per stage is constant in the serial case two inputs per stage.
Connect the count-up ripple counter shown in Fig. Set data switch SW1 from logic 0 to logic 1 clear all flip-flops. Now connect CLK to a pulse generator in your pencil box J-K flip-flops in 74LS76 are negative edge triggered and start counting by pushing the pulser button. Continue the process and record the output of each transition in a truth table. Does it count correctly?